1. Field of the Invention
The present invention relates to bit line structure for a semiconductor memory device, and more particularly, it relates to structure of bit lines for preventing information signal readout errors in a dynamic type semiconductor memory device.
2. Description of the Prior Art
FIG. 1 shows an exemplary structure of a general semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device comprises a memory cell array 100 which is formed by a plurality of memory cells arrayed in the form of a matrix of rows and columns, an address buffer 101 which receives externally supplied address signals Ext.ADD to output internal row address signals A.sub.0 to A.sub.n and internal column address signals B.sub.0 to B.sub.m, a row decoder 102 which receives the internal row address signals A.sub.0 to A.sub.n to select a corresponding row from the memory cell array 100, a (I/O and sense amplifier) part 104 which is formed by a sense amplifier portion for detecting and amplifying information appearing on respective columns of the memory cell array 100 and an I/O portion for connecting the information amplified by the sense amplifier portion to an output buffer 103, a column decoder 105 which selects a column from the memory cell array 101 in response to the internal column address signals B.sub.0 to B.sub.m to transmit information on the selected column to the output buffer 103 through the I/O portion of the (I/O and sense amplifier) part 104 and the output buffer 103 which receives the information on the column selected by the column decoder 105 through the I/O part to output the same. It is to be noted that FIG. 1 shows only a data read system of the semiconductor memory device.
FIG. 2 shows the structure of a bit line part of the conventional dynamic type semiconductor memory device, which bit line part corresponds to a region enclosed by broken lines in FIG. 1.
FIG. 2 only shows two word lines WL.sub.0 and WL.sub.1, two bit lines BL and BL, two dummy word lines DWL.sub.0 and DWL.sub.1 and a sense amplifier SA, for convenience of illustration.
A column of memory cells are connected to each of the word lines WL.sub.0 and WL.sub.1 while a row of memory cells are connected to each of the bit lines BL and BL.
The bit lines BL and BL are paired to form the so-called folded bit line. Therefore, memory cells are provided at intersections between the word line WL.sub.0 and the bit line BL and between the word line WL.sub.1 and the bit line BL respectively. Although not shown in the figure, memory cells are similarly provided at intersections between the bit line BL and alternate word lines as well as between the bit line BL and alternate word lines.
A sense amplifier SA for detecting and amplifying a potential difference on the paired bit lines BL and BL is formed by cross-coupled NMOS transistors. This sense amplifier SA is activated in response to a sense amplifier activating signal .phi..sub.S, to pull down a lower potential of one of the bit lines BL and BL to a low potential (ground potential).
The sense amplifier activating signal .phi..sub.S is supplied to the gate of a switching transistor Q.sub.2. One conducting terminal of the switching transistor Q.sub.2 is connected to the ground potential and the other conducting terminal is connected to first conducting terminals of both MOS transistors of the sense amplifier SA. Second conducting terminals of the MOS transistors of the sense amplifier SA are connected with the bit lines BL and BL respectively.
The dummy word lines DWL.sub.0 and DWL.sub.1 are provided with dummy cells DC.sub.0 and DC.sub.1 for supplying a reference potential during operation of the sense amplifier SA. The dummy cell DC.sub.0 is provided at the intersection between the dummy word line DWL.sub.0 and the bit line BL, and the dummy cell DC.sub.1 is provided at the intersection between the dummy word line DWL.sub.1 and the bit line BL.
Each of memory cells MC.sub.0 and MC.sub.1 for storing information is a one-transistor/one-capacitor type memory cell which has a memory cell capacitor CS for storing information in the form of charges and a transfer gate TG being turned on/off in response to the word line potential for connecting the memory cell capacitor CS to the bit line BL or BL.
Each of the dummy cells DC.sub.0 and DC.sub.1 is structured similarly to the memory cell, and stores a quantity of charge equal to half that stored in the memory cell capacitor in a high-level state.
Transfer gates Q.sub.1 and Q.sub.1 ' are provided in order to connect a bit line pair selected in response to a column address signal from the column decoder 105 to a pair of data input/output lines I/O and I/O. The transfer gate Q.sub.1 connects the bit line BL to the data input/output line I/O, and the transfer gate Q.sub.1 ' connects the bit line BL to the data input/output line I/O. These transfer gates Q.sub.1 and Q.sub.1 ' are supplied at their gates with the output of the column decoder 105.
With reference to FIG. 1, description is now briefly made of an operation for data reading.
Each bit line is precharged at the potential V.sub.CC until a word line is selected and the potential of the selected word line rises. Then, when a word line (e.g., WL.sub.0) is selected by the output of the row decoder 102, the dummy word line DWL.sub.1 is simultaneously selected so that the memory cell MC.sub.0 is connected to the bit line BL.sub.1 and the dummy cell DC.sub.1 is connected to the bit line BL.sub.1. The dummy cells DC.sub.1 and DC.sub.0 store quantities of charges of 1/2 V.sub.CC C.sub.S, where V.sub.CC is a supply potential and C.sub.S is a capacitance of a memory capacitor.
A potential responsive to the information stored in the memory cell MC.sub.0 appears on the bit line BL.sub.1, which potential on the bit line BL.sub.1 is higher or lower than a potential on the bit line BL.sub.1, whereby a potential difference is caused between the bit lines BL.sub.1 and BL.sub.1. Then the sense amplifier activating signal .phi..sub.S goes high and the transfer gate Q.sub.2 enters an ON state, thereby to activate the sense amplifier SA. Thus, the potential difference between the paired bit lines BL.sub.1 and BL.sub.1 is amplified (the one of the bit lines having lower potential is discharged to the ground potential level). Then the transfer gates Q.sub.1 and Q.sub.1 ' enter ON states by the output of the column decoder 105, so that the bit lines BL.sub.1 and BL.sub.1 are connected to the data input/output lines I/O and I/O respectively, to read out the data.
The potentials appearing on the bit lines may be calculated as described below.
FIG. 3 illustrates parasitic capacitance present on each bit line. Each of the bit lines BL.sub.0 to BL.sub.2 and BL.sub.0 to BL.sub.2 has capacitance C.sub.1 with respect to the ground potential (fixed potential), capacitance C.sub.2 with respect to the bit line paired with the same and capacitance C.sub.3 with respect to the bit line of the adjacent bit line pair. It is assumed here that each bit line has length l and the memory cell capacitor CS has capacitance C.sub.s.
Each memory cell stores charges of C.sub.s V.sub.CC (V.sub.CC writing) in "H" storage and 0 (0 V writing) in "L" storage. "V.sub.CC writing" and "0 V writing" indicate potentials supplied to the bit lines in information writing respectively.
Each dummy cell for supplying the reference potential to the bit line stores charges of 1/2 C.sub.s V.sub.CC (1/2 V.sub.CC writing in capacitance C.sub.s etc.).
Each bit line is precharged at the potential V.sub.CC until a word line is selected by the output of the row decoder 102 and the potential of the selected word line rises at a potential exceeding V.sub.CC.
With reference to FIG. 3, consider that the memory cells connected to the bit line BL.sub.1 are selected and dummy cells are connected to the bit line BL.sub.1. In this case, a dummy word line is so selected that the selected memory cells are connected to one of paired bit lines and the dummy cells are connected to the other bit line.
When the selected word line rises at a potential exceeding V.sub.CC, potentials on the bit lines BL.sub.1 and BL.sub.1 are provided as follows:
In case of "L" reading: ##EQU1##
In case of "H" reading": ##EQU2## where .DELTA.V(BL.sub.0), .DELTA.V(BL.sub.1), .DELTA.V(BL.sub.1) and .DELTA.V(BL.sub.2) represent potential variations appearing on the bit lines BL.sub.0, BL.sub.1, BL.sub.1 and BL.sub.2 respectively.
Since precharge levels of the bit lines BL.sub.1 and BL.sub.1 are equally at V.sub.CC, the potential difference between the bit lines BL.sub.1 and BL.sub.1 is obtained from the expressions (1)-(3) and (2)-(3) as follows: ##EQU3## Sign "+" indicates "H" reading and sign "-" indicates "L" reading.
In the above expression (4), the first term in the right side of the equation represents original readout potential difference, and the second term in the right side expresses noise components from the bit lines BL.sub.0 and BL.sub.2 of the adjacent bit line pairs through capacitive coupling.
FIG. 4 shows exemplary changes of bit line potentials in data reading. Shown in FIG. 4 are voltage waveforms in such case that "L" is read on a bit line BL and "L" is read on a bit line BL of an adjacent bit line pair.
Lowering in readout voltage on a bit line caused by capacitive coupling noise with respect to an adjacent bit line pair is also described in IBM Journal of Research and Development, Vol. 29, No. 3, May 1985, pp. 277-288 by Peter E. Cottrel et al. This literature shows that the readout voltage is reduced in the ratio of ##EQU4## (K: proportional constant) to 1.
When a semiconductor memory device is increased in storage capacitance and the memory size is decreased, the bit line pitch is also reduced. In this case, the interval between adjacent bit line pairs is also reduced and the capacitance C.sub.3 between the bit line pairs is increased, whereby the second term in the right side of the expression (4) is increased. Namely, influence by potentials in bit lines of adjacent bit line pairs is increased, whereby readout voltage on the bit lines may be extremely damaged and potential difference .DELTA.V.sub.S on the bit line pair may be reduced. Thus, the sense amplifier SA cannot correctly detect and amplify the potential difference on the bit line pair, whereby the readout margin is lowered and the soft error rate is deteriorated, leading to a malfunction.
Since the conventional dynamic type semiconductor memory device is in the aforementioned structure, readout voltage difference is reduced by capacitive coupling noises between adjacent bit line pairs as the semiconductor memory device is implemented with higher density of integration which causes capacitance between adjacent bit lines to be increased, whereby the soft error rate is deteriorated and the readout margin is lowered, leading to a malfunction.
Japanese Patent Laying-Open Gazette No. 60-254489 described structure of reducing noise components caused by capacitive coupling between adjacent bit line pairs. In this prior art example, two bit lines forming a bit line pair are intersected with alternate bit line pairs so that the two bit lines are alternately adjacent to bit lines of adjacent bit line pairs. However, although noise components caused by capacitive coupling can be reduced with respect to bit line pairs having intersections, since such intersections of the bit lines are provided with respect to alternate bit line pairs, noises caused by capacitive coupling cannot be reduced with respect to bit line pairs provided with no such intersections. Namely, no consideration is made on reduction of noises in the bit line pairs provided with no intersections.
Japanese Published Patent Application (KoKai) No. 62-51096 describes a memory device formed by alternately arranged bit line pairs intersected in even portions and bit line pairs intersected in odd portions. Although this prior art example shows a memory device in which the bit lines are precharged at the V.sub.CC level, no consideration is made on presence of dummy cells. Further, no consideration is made on unbalanced capacitance distribution in a pair of bit lines caused by an intersection and increase in bit line length caused by provision of such intersections.